With the explosive growth of data center traffic and the continuous surge in computing power demand, coherent optical modules are evolving toward higher speed, lower power consumption, and smaller form factor. Coherent detection and Co-packaged Optics (CPO) technology, leveraging the core advantage of "photonic-electronic co-packaging", has become a key solution to break through the performance bottlenecks of traditional optical modules. As the core carrier of CPO devices, silicon photonics wafers adopt a double-sided integration design (optically active/passive devices integrated on the front side, and driver & control circuits integrated on the back side), which greatly improves device integration and performance but also imposes rigorous challenges on wafer-level testing technology. For silicon photonics customers, accurately grasping the technical difficulties of CPO double-sided wafer testing and clarifying its importance are the core prerequisites for ensuring the mass production yield of CPO devices, controlling costs, and enhancing the competitiveness of end products.
I. Core Importance of CPO Double-Sided Wafer Testing for Silicon Photonics Customers
CPO double-sided wafer testing is not a simple "upgrade of conventional wafer testing", but a key link running through the entire process of CPO device R&D, mass production, and cost control. Its importance is directly related to the core interests of silicon photonics customers, specifically reflected in the following three dimensions:
(1) Guarantee Mass Production Yield and Reduce End-Cost Losses
CPO devices adopt a double-sided integration architecture. The optical devices on the front side of the wafer (such as grating couplers, waveguides, modulators) and the electrical chips on the back side (such as driver chips, TIA chips) need to achieve high-precision collaborative work. Defects in either single side or interconnection deviations between the two sides will lead to final device failure. If comprehensive testing is not completed at the wafer level, defective wafers will flow into subsequent packaging processes, which not only increases additional costs such as packaging materials and labor but also causes significant cost losses due to the inability to rework failed devices after packaging. For silicon photonics customers, pre-screening qualified wafers through wafer-level testing can move yield control forward, significantly reduce the unit device cost during mass production, and enhance product market competitiveness.
(2) Verify Integrated Performance and Mitigate End-Application Risks
The core value of CPO technology lies in "optoelectronic synergy and efficiency enhancement", and its performance advantages depend on the collaborative optimization of optical, electrical, and thermal multi-physics fields. Double-sided wafer testing not only needs to detect the performance parameters of individual optical and electrical devices but also verify the collaborative working performance after double-sided integration (such as optoelectronic signal coupling efficiency, response speed of electrical drive signals to optical modulation, and performance stability under high-temperature conditions). If wafer-level integrated performance testing is skipped and testing is only conducted after device packaging, the discovery of substandard integrated performance will result in rework or scrapping of the entire batch of products, which not only delays the delivery cycle but also may affect the customer's reputation in the end market due to substandard product performance. By verifying integrated performance in advance through wafer-level testing, silicon photonics customers can effectively mitigate performance risks in end applications and ensure product delivery quality.
(3) Support R&D Iteration and Accelerate Technology Implementation
Currently, CPO technology is still in a stage of rapid iteration. Silicon photonics customers need to continuously optimize the double-sided integration process and improve device structures to enhance performance. Wafer-level testing can provide accurate data support for process optimization during the R&D phase: by testing wafers under different process parameters, analyzing the correlation between test data and process parameters, it is possible to quickly identify process shortcomings (such as double-sided lithography alignment deviations, excessive resistance of interconnection metal layers, etc.) and guide process iteration and optimization. Meanwhile, wafer-level testing enables rapid verification of new device structures, shortens the R&D cycle, helps silicon photonics customers seize technological opportunities, and gain an advantage in the fierce market competition.
II. Core Technical Challenges of CPO Double-Sided Wafer Testing
Compared with traditional single-sided wafer testing, CPO double-sided wafer testing faces multiple challenges such as "double-sided collaborative testing, multi-physics field coupling, high-precision alignment, and signal interference suppression". The specific technical difficulties can be summarized into the following four categories:
(1) Double-Sided Testing Compatibility Challenge: Conflict Between Test Resources and Wafer Structure
The front side of a CPO double-sided wafer is an optical device integration area, requiring optical probes for optical signal input/output testing; the back side is an electrical chip integration area, requiring electrical probes for electrical signal excitation and acquisition. Traditional wafer testing platforms are mostly designed for single-sided testing and cannot achieve precise deployment of double-sided probes simultaneously—testing the front side first and then the back side may cause wafer damage or surface contamination during the wafer flipping process; adopting simultaneous double-sided testing may lead to mutual interference between the mechanical structure and probe layout of the prober (such as the optical path of optical probes being blocked by electrical probes, and the mechanical support structure of electrical probes affecting optical alignment). In addition, the electrical chip integration area on the back side of the wafer may have structures such as metal wiring and bumps, which further limit the deployment space of electrical probes and increase the difficulty of double-sided testing compatibility. For silicon photonics customers, how to select or customize a platform compatible with double-sided testing and balance testing efficiency and testing safety is the primary issue to be resolved.
(2) High-Precision Alignment Challenge: Guarantee of Testing Accuracy for Double-Sided Device Interconnection
The front-side optical devices and back-side electrical devices of CPO double-sided wafers are interconnected through Through-Silicon Vias (TSVs), and the alignment accuracy of TSVs directly affects the transmission efficiency of optoelectronic signals. Wafer-level testing needs to accurately locate TSV interconnection positions to ensure that optical probes and electrical probes are in precise contact with the test pads of front-side optical devices and back-side electrical devices respectively; otherwise, test signal distortion will occur, failing to truly reflect device performance. However, in actual testing, wafer warpage, mechanical vibration of the testing platform, and thermal expansion and contraction of the wafer caused by temperature changes will all affect alignment accuracy. Especially for large-size silicon photonics wafers (such as 8-inch and 12-inch), the warpage at the wafer edge is more significant, and the alignment difficulty is significantly increased. In addition, during double-sided testing, the alignment references of the front and back sides must be consistent; if there is a reference deviation, the test data will deviate greatly from the actual device performance, failing to provide an effective basis for yield control.
(3) Multi-Parameter Collaborative Testing Challenge: Synchronous Acquisition and Analysis of Optical, Electrical, and Thermal Signals
The performance of CPO devices is affected by the coupling of optical, electrical, and thermal multi-physics fields: the stability of electrical drive signals will affect optical modulation efficiency, the transmission loss of optical signals will affect the demodulation accuracy of electrical signals, and thermal diffusion under high-temperature conditions will deteriorate both optical and electrical performance. Therefore, wafer-level testing needs to synchronously collect optical parameters (such as insertion loss, polarization-dependent loss, modulation bandwidth), electrical parameters (such as drive current, response speed, leakage current), and thermal parameters (such as device temperature distribution, thermal resistance), and analyze the coupling relationship between multiple parameters. However, traditional testing platforms are mostly designed for single-parameter testing, and the synchronization of optical, electrical, and thermal testing systems is poor, making it difficult to achieve real-time collaborative acquisition of multiple parameters. At the same time, the massive data generated by multi-parameter testing requires efficient analysis algorithms for support; if data processing is not timely or the analysis method is inappropriate, it will be impossible to quickly locate the root cause of device defects, affecting testing efficiency. For silicon photonics customers, the accuracy and efficiency of multi-parameter collaborative testing directly determine the effectiveness of yield control.
(4) Signal Interference Suppression Challenge: Noise Control in Testing Environment and Test Links
The operating rate of CPO devices has evolved to 1.6 Tbps and above, and high-frequency test signals are extremely sensitive to noise. During double-sided testing, signal interference mainly comes from two aspects: one is testing environment interference, such as electromagnetic radiation of the testing platform, external light (affecting optical testing accuracy), and temperature fluctuations; the other is test link interference, such as coupling loss between optical probes and optical devices, contact resistance and parasitic capacitance of electrical probes, and signal attenuation and crosstalk of test cables. In addition, during double-sided testing, the laser signal of front-side optical testing may be transmitted to the back-side electrical test link through the wafer, generating photoelectric crosstalk; the high-frequency signals of back-side electrical testing may also interfere with the acquisition of front-side optical signals. How to optimize test link design (such as adopting low-loss optical probes and high-frequency electrical probes), construct a shielded testing environment, suppress multi-link signal interference, and ensure the integrity of test signals is a key difficulty in improving the accuracy of test data, as well as a core demand of silicon photonics customers for ensuring testing quality.
III. ETERNAL Launches Double-Sided Wafer Testing System
Eternal’s Double-Sided Wafer Optoelectronic Testing System is an innovative solution specifically designed to meet the demand for simultaneous optoelectronic testing of both the top and bottom sides of wafers. Breaking the efficiency bottleneck of traditional single-sided testing, it realizes optical coupling and synchronous electrical-optical testing through an innovative dual-sided parallel architecture of "top optical testing + bottom electrical testing" or "top electrical testing + bottom optical testing". It is a breakthrough testing solution for advanced semiconductor fields such as Silicon Photonics (SiPh) and CPO co-packaged optics.
Product Features
• High-density pump ball automatic probing with quantifiable and controllable probing force
• Compatible with top-optics bottom-electronics and top-electronics bottom-optics configurations, supporting multiple double-sided testing modes
• Compatible with most functions of traditional electrical probers and optoelectronic probers
• Customizable for 8~12-inch wafer sizes
• Machine vision automatic calibration
• Optional end-to-end testing solution services
Product Applications
This system is mainly targeted at CPO wafer testing scenarios, supporting simultaneous dual-sided optoelectronic combined testing in configurations of "top optoelectronic testing + bottom electrical testing" or "top electrical testing + bottom optical testing"; optical testing is compatible with SMF, Lens Fiber, and FA configurations; electrical testing is compatible with probe holders or probe cards, meeting the testing needs of various application scenarios in R&D and mass production.
Summary
For silicon photonics customers, CPO double-sided wafer testing is a core link to ensure the mass production yield of CPO devices, control costs, and mitigate application risks. Its importance is increasingly prominent with the large-scale application of CPO technology. The core technical difficulties such as double-sided testing compatibility, high-precision alignment, multi-parameter collaborative testing, and signal interference suppression not only test the hardware performance of the testing platform but also impose rigorous requirements on the systematic design of the testing solution. In the future, with the continuous breakthroughs in testing technology (such as the application of high-precision double-sided probers, multi-parameter synchronous testing systems, and intelligent noise suppression algorithms), the efficiency and accuracy of CPO double-sided wafer testing will continue to improve, providing strong support for the implementation and large-scale mass production of CPO technology by silicon photonics customers. Silicon photonics customers need to lay out test technology reserves in advance, strengthen collaboration with test equipment suppliers, and optimize test solutions according to the design characteristics of their own CPO devices to take the initiative in technological and market competition.