With the explosive growth of data center traffic and the continuous increase in computing power demand, coherent optical modules are evolving towards higher speeds, lower power consumption, and smaller sizes. Leveraging the core advantage of "optoelectronic co-packaging," CPO technology has emerged as a key solution to break through the performance bottleneck of traditional optical modules.

As the core carrier of CPO devices, the silicon photonic wafer's dual-sided integration design (integrating optical active/passive devices on the front side and driving and control circuits on the back side) significantly enhances the integration level and performance of the devices. However, it also poses severe challenges to wafer-level testing technology. For silicon photonic customers, accurately grasping the technical difficulties of CPO dual-sided wafer testing and clarifying its testing importance are core prerequisites for ensuring mass production yield of CPO devices, controlling costs, andenhancing the competitiveness of end products.

PART 01  The importance of Dual-sided Wafer Test

CPO dual-sided wafer testing is not a mere "upgrading of conventional wafer testing", but a crucial aspect that permeates the entire process of CPO device research and development, mass production, and cost control. Its significance is directly tied to the core interests of silicon photonics customers, specifically manifested in the following two dimensions:

• Ensure mass production yield and reduce terminal cost losses

The CPO device adopts a dual-sided integration architecture, where the optical components on the front side of the wafer (such as grating couplers, waveguides, and modulators) and the electrical chips on the back side (such as driver chips and TIA chips) must work in high-precision coordination. Any defects in the components on one side or deviations in the interconnection between the two sides will lead to the ultimate failure of the device.

If comprehensive testing is not completed at the wafer level, defective wafers will proceed to subsequent packaging stages, which will not only increase additional costs such as packaging materials and labor, but also result in significant cost losses due to the inability to rework failed devices after packaging. For silicon photonics customers, screening qualified wafers in advance through wafer-level testing can advance yield control, significantly reduce the cost per device in the mass production stage, and enhance product market competitiveness.

• Support R&D iteration and accelerate the process of technology implementation

Currently, CPO technology is still in a rapid iteration stage, and silicon photonics customers need to continuously optimize the dual-side integration process and improve device structures to enhance performance. Wafer-level testing can provide precise data support for process optimization during the research and development stage: by testing wafers under different process parameters and analyzing the correlation between test data and process parameters, it is possible to quickly identify process shortcomings (such as dual-side lithography alignment deviations, excessive resistance in interconnect metal layers, etc.), guiding process iteration optimization.

Meanwhile, wafer-level testing enables rapid verification of novel device structures, shortens the research and development cycle, and helps silicon photonics customers seize technological opportunities, thereby gaining an advantage in fierce market competition.

PART 02  The core technical challenges of CPO Dual-sided Wafer Test

Compared to traditional single-sided wafer testing, CPO dual-sided wafer testing faces multiple challenges such as "dual-sided collaborative testing, multi-physics field coupling, high-precision alignment, and signal interference suppression". The specific technical difficulties can be summarized into the following five categories:

• The compatibility challenge of dual-side testing: conflict between testing resources and wafer structure

The front side of the CPO dual-sided wafer serves as the optical device integration area, requiring optical probes for input/output testing of optical signals; the back side serves as the electrical chip integration area, requiring electrical probes for excitation and acquisition of electrical signals.

Traditional wafer testing platforms are mostly designed for single-sided testing, which cannot simultaneously achieve precise deployment of dual-sided probes. If testing is conducted on the front side first and then on the back side, wafer damage or surface contamination may occur during the wafer flipping process. If dual-sided testing is adopted, the mechanical structure of the probe station and probe layout are prone to mutual interference (such as the optical path of optical probes being blocked by electrical probes, or the mechanical support structure of electrical probes affecting optical alignment).

Furthermore, the electrical chip integration area on the backside of the wafer may contain structures such as metal wiring and bumps, which further restrict the deployment space for electrical probes and increase the difficulty of achieving compatibility for dual-side testing. For silicon photonics customers, the primary issue to be addressed is how to select or customize a platform compatible with dual-side testing, balancing testing efficiency and testing safety.

• Verify integration performance and mitigate risks in end-user applications

The front side of the CPO dual-sided wafer serves as the optical device integration area, requiring optical probes for input/output testing of optical signals; the back side serves as the electrical chip integration area, requiring electrical probes for excitation and acquisition of electrical signals. Traditional wafer testing platforms are mostly designed for single-sided testing, unable to simultaneously achieve precise deployment of dual-sided probes. If testing the front side first and then the back side, wafer damage or surface contamination may occur during the flipping process; if simultaneous dual-sided testing is adopted, the mechanical structure of the probe station and probe layout are prone to mutual interference (such as the optical path of optical probes being blocked by electrical probes, or the mechanical support structure of electrical probes affecting optical alignment).

Furthermore, the electrical chip integration area on the backside of the wafer may contain structures such as metal wiring and bumps, which further restrict the deployment space for electrical probes and increase the difficulty of achieving compatibility for dual-side testing. For silicon photonics customers, the primary issue to be addressed is how to select or customize a platform compatible with dual-side testing, balancing testing efficiency and testing safety.

• High-precision alignment challenge: ensuring test accuracy for interconnection of dual-sided devices

The front-side optical devices and back-side electrical devices of CPO dual-sided wafers are interconnected through through-silicon vias (TSVs), and the alignment accuracy of TSVs directly affects the transmission efficiency of optoelectronic signals.

Wafer-level testing requires precise positioning of TSV interconnect locations to ensure accurate contact between optical probes and electrical probes with the test pads of front-side optical devices and back-side electrical devices, respectively. Otherwise, it will lead to test signal distortion and fail to truly reflect the device performance. However, in actual testing, wafer warping, mechanical vibration of the test platform, and thermal expansion and contraction of the wafer caused by temperature changes can all affect alignment accuracy.

Especially for large-sized silicon photonic wafers (such as 8-inch and 12-inch wafers), the degree of warping at the wafer edge is greater, significantly increasing the difficulty of alignment. Furthermore, during the dual-side testing process, the alignment benchmarks for the front and back sides must be consistent. Any deviation in benchmarks will lead to significant discrepancies between test data and actual device performance, making it impossible to provide an effective basis for yield control.

• Multi-parameter collaborative testing challenge: synchronous acquisition and analysis of optical, electrical, and thermal signals

The performance of CPO devices is influenced by the coupling of multiple physical fields: optical, electrical, and thermal. The stability of the electrical drive signal affects the efficiency of optical modulation, while the transmission loss of the optical signal impacts the demodulation accuracy of the electrical signal. Thermal diffusion under high-temperature conditions simultaneously deteriorates both optical and electrical performance.

Therefore, wafer-level testing requires simultaneous acquisition of optical parameters (such as insertion loss, polarization-dependent loss, modulation bandwidth), electrical parameters (such as drive current, response speed, leakage current), and thermal parameters (such as device temperature distribution, thermal resistance), as well as analysis of the coupling relationships among multiple parameters.

However, traditional test platforms are mostly designed for single-parameter testing, and the synchronization of optical, electrical, and thermal test systems is poor, making it difficult to achieve real-time collaborative acquisition of multiple parameters. Simultaneously, the massive data generated by multi-parameter testing requires efficient analysis algorithms. If data processing is not timely or analysis methods are improper, it will be impossible to quickly locate the root cause of device defects, affecting test efficiency. For silicon photonics customers, the accuracy and efficiency of multi-parameter collaborative testing directly determine the effectiveness of yield control.

• The challenge of signal interference suppression: noise control in testing environments and testing links

The operating rate of CPO devices has evolved to 1.6 Tbps and beyond, and high-frequency test signals exhibit extremely high sensitivity to noise. During dual-side testing, signal interference primarily stems from two sources: firstly, test environment interference, such as electromagnetic radiation from the test platform, external light (affecting optical test accuracy), and temperature fluctuations; secondly, test link interference, including coupling loss between optical probes and optical components, contact resistance and parasitic capacitance of electrical probes, and signal attenuation and crosstalk in test cables.

Furthermore, in dual-side testing, the laser signal from the front-side optical testing may be conducted through the wafer to the back-side electrical testing circuit, resulting in optoelectronic crosstalk. The high-frequency signal from the back-side electrical testing may also interfere with the acquisition of front-side optical signals. Optimizing the design of the testing circuit (such as using low-loss optical probes and high-frequency electrical probes), constructing a shielded testing environment, and suppressing multi-channel signal interference to ensure the integrity of the testing signals are key challenges in improving the accuracy of test data, and are also the core demands of silicon photonics customers to ensure testing quality.

PART 03  ETERNAL-Dual-Side Wafer-Level Optoelectronic Test System

The dual-side wafer optoelectronic testing system from Eternal represents a novel solution, specifically designed to cater to the need for simultaneous optoelectronic testing of both the Top and Bottom sides of wafers. It overturns the efficiency bottleneck inherent in traditional single-side testing, achieving optical coupling and synchronous electrical and optical testing through an innovative dual-side parallel architecture of either "upper side optical testing + lower side electrical testing" or "upper side electrical testing + lower side optical testing". This represents a breakthrough testing solution for advanced semiconductor fields such as CPO (Common Packaging Optics).

Product Features

• High-density bump ball automatic puncture, with quantifiable and controllable puncture force

• Compatible with both top-down and bottom-up configurations, and supports various dual-side testing configurations

• Compatible with traditional electrical probe stations and optoelectronic probe stations

• Wafer size ranging from 8 to 12 inches can be customized

• Fully automatic calibration of machine vision

• Non-contact loading and unloading

• Optional end-to-end testing solution service

Product Application

The system primarily targets CPO wafer test application scenarios, supporting dual-sided parallel optoelectronic joint testing, either "upper-side optoelectronic testing + lower-side electrical testing" or "upper-side electrical testing + lower-side optoelectronic testing". The optical testing is compatible with various forms such as SMF, Lens Fiber, and FA; the electrical testing is compatible with probe heads or probe cards, meeting the testing needs of various application scenarios in research and development as well as mass production.

PART 04

For silicon photonics customers, CPO dual-side wafer testing is a core aspect in ensuring mass production yield of CPO devices, controlling costs, and mitigating application risks. Its importance has become increasingly prominent with the large-scale application of CPO technology. However, core technical challenges such as dual-side testing compatibility, high-precision alignment, multi-parameter collaborative testing, and signal interference suppression not only test the hardware performance of the testing platform but also impose stringent requirements on the systematic design of the testing scheme.

In the future, with continuous breakthroughs in testing technology (such as the application of high-precision dual-side probe stations, multi-parameter synchronous testing systems, and intelligent noise suppression algorithms), the efficiency and accuracy of CPO dual-side wafer testing will continue to improve, providing strong support for the implementation and large-scale production of CPO technology for silicon photonics customers. Silicon photonics customers need to plan ahead for testing technology reserves, strengthen collaboration with testing equipment suppliers, and optimize testing schemes based on the design characteristics of their own CPO devices, in order to gain the upper hand in technological and market competition.

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Dual-Side Wafer-Level Optoelectronic Test System are available for consultation and customization

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